[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[amibroker] ARRAY PROCESSING



PureBytes Links

Trading Reference Links

Directly below, I have copied the discussion of ARRAYS from the Amibroker user manual. 

 Below this ARRAY explanation, is what AMD says about some of their CPU processor's ability to process ARRAYS.

When AFL is evaluating statement like this ( High + Low )/2 it does not need to re-interpret this code for each bar. Instead it takes the High ARRAY and Low ARRAY and adds corresponding array elements in single stage. In other words + operator (and other operators too) work on arrays at once and it is executed at full compiled-code speed, then the resulting array (each element of it) is divided by 2 also in single stage.

Let's look into the details - see fig 2.. When AFL engine looks at the ( High + Low )/2 it first takes High (1) and Low (2) arrays and produces (in single compiled step) the temporary array (3). Then it creates the final array (4) by dividing each element of temporary array by two. This result is assigned to myVariable

Bar
1
2
3
4
5
6
7
8
9
10
1 High (built-in array)
1,24
1,27
1,25
1,29
1,25
1,29
1,35
1,35
1,37
1,29
2 Low (built-in array)
1,20
1,21
1,19
1,20
1,21
1,24
1,30
1,28
1,31
1,27
3 High+Low (temporary array created during evaluation)
2,44
2,48
2,44
2,49
2,46
2,53
2,65
2,63
2,68
2,46
4 ( High+Low ) /2 (gets assigned to MyVariable)
1,22
1,24
1,22
1,245
1,23
1,265
1,325
1,315
1,34
1,23

Fig 2. AFL steps when processing ( High + Low ) /2

Below here is the AMD information.
====================================================
An advanced HyperTransport link:
__
This feature dramatically improves the I/O bandwidth, enabling much faster access to peripherals such as hard drives, USB 2.0, and Gigabit Ethernet cards.

__
HyperTransport technology enables higher performance due to a reduced I/O interface throttle.

Large level one (L1) and level 2 (L2) on-die cache:

__With 128 Kbytes of L1 cache and 512K or 1MB of L2 cache per core, the AMD Athlon 64 and Athlon 64 X2 processors are able to excel at performing matrix calculations on arrays.

__Programs that use intensive large matrix calculations will benefit from fitting the entire matrix in the L2 cache.
 
=====================================================
 
Does anyone know if this AMD level-one and level-two on-die cache will improve Amibroker's speed when it computes hundreds of timeframes of RSI and hunderds of timeframes of STOCHK, all within one custom indiocator window??  Rightnow, my 2001 Athlon1000 with 512 MB of NONDDR Ram can plot two line sof this on the screen, but I have difficulty moving the vertical line to the next EOD bar.  TIA Ron D.
 
 
 


Please note that this group is for discussion between users only.

To get support from AmiBroker please send an e-mail directly to
SUPPORT {at} amibroker.com

For other support material please check also:
http://www.amibroker.com/support.html





YAHOO! GROUPS LINKS